1. Field of the Invention
The present invention relates to a cache memory control method used in a shared-bus multiprocessor system. More specifically, it relates to a snoop cache memory control system which ensures the consistency of data among cache memories connected through the common bus to the shared memory.
2. Description of the Prior Art
In the field of a shared-bus multiprocessor system where a plurality of processors are connected through the shared bus to the shared memory, it is well known that each processor has its own cache memory to speed up processing and to reduce the bus traffic. This method requires a mechanism which, when data is written to one of a plurality of cache memories, ensures the consistency of data among the cache memories. This type of shared bus multiprocessor system ensures consistency by allowing the cache memory of each processor to monitor the bus transactions of the other cache memories. A cache memory like this is called a snoop cache memory. Several snoop cache memory control methods have been proposed to manage cache memory.
One of the conventional snoop cache memory control methods is as follows. When a cache miss occurs in a cache memory and some other cache memory has a block containing the missed data, this method transfers the block, not from the slow-access shared memory, but directly from the cache memory containing it, thus minimizing the data transfer overhead.
In this case, because there may be one or more cache memories where a block containing the missed data is stored, it is necessary to determine a cache memory from which the missed data is to be transferred to the cache memory where the cache miss occurred. One of the methods for accomplishing this is to pre-define the cache memory acting as the owner of a block. This method is employed in the snoop cache memory of the Berkeley scheme or Dragon scheme introduced, for example, in the following documents: James Archibald, et al., "Cache Coherence Protocols: Evaluation Using a Multiprocessor Simulation Model", acm Transactions on Computer Systems, 1986, November, Vol. 4, Number 4, pp. 273-298. If data in the block is modified and it does not match that in the shared memory, the cache memory is responsible for writing data back to the shared memory when it expels the block.
That is, the owner cache memory, which has a block containing data cache-missed (not detected in the cache) by some other cache memory, must transfer the block to that cache memory. In addition, when the owner cache memory expels a modified block, it must write back the block to the shared memory.
However, the method described above has the following problems. First, when a cache memory expels a block it owns (that is, the owner of the block) and, after that, a cache miss occurs for that block in some other cache memory, that cache memory must transfer the block from the shared memory.
For example, once the owner cache memory expels a block, some other non-owner cache memory having the same block cannot transfer the block to another cache memory because only the owner has the block transfer authority. As a result, a cache miss in any of the cache memories under this condition would cause the block to be transferred from the shared memory, increasing the block transfer overhead.
Second, when a cache memory modifies a block it owns and then expels the block, it must write the block back to the shared memory. So, when a non-owner cache memory, which has a block already written back to the shared memory by the owner, modifies that block, it must write the block back to the shared memory again. The non-owner cache memory does this in order to match the data in the cache memory with that in the shared memory. That is, the block written back by the owner is replaced by the block written back by the non-owner cache memory, meaning that the write-back by the owner is wasteful.
In view of the foregoing, there has been a need for a snoop cache memory control system designed around the ownership of a block of data in which a block is transferred between cache memories, if possible, with the minimum access to the shared memory.